The present invention relates to an edge-triggered D-Flip-Flop circuit, having a master circuit and a slave circuit. Edge-triggered D-Flip-Flop circuit according to claim 6, characterised in that the pass-transistors are enhancement type MOSFETs. Edge-triggered D-Flip-Flop circuit according to claim 5, characterised in that the pass-transistors are MOSFETs (metal oxide semiconductor field effect transistors).ħ. Edge-triggered D-Flip-Flop circuit according to any of claims 1 to 4, characterised in that the master switch (T1) and the slave switch (T2) are pass-transistors.Ħ.
Edge-triggered D-Flip-Flop circuit according to claim 2 or 3, characterised in that a reset switch (T5) is provided with one end connected to the output terminal of the second inverter (I2) and another end connected to ground potential (GND).ĥ. Edge-triggered D-Flip-Flop circuit according to claim 2, characterised in that a set switch (T4) is provided with one end connected to the input terminal of the second inverter (I2) and another end connected to ground potential (GND).Ĥ.
Edge-triggered D-Flip-Flop circuit according to claim 1, characterised in that means to set (S) and reset (R) an information stored in the slave circuit are provided.ģ. Edge-triggered D-Flip-Flop circuit having a master circuit (MA) and a slave circuit (SL), characterised in that said master circuit (MA) comprises a master switch (T1) controlled by a clock signal (C) and connected with one end to a data input terminal (D) and comprising a first inverter having an input terminal and an output terminal, said input terminal being connected to said master switch and said slave circuit (SL) comprises a slave switch (T2) controlled by said clock signal (C) and connected to said output terminal of said first inverter (I1), a second inverter (I2) having an input terminal and an output terminal (Q), said input terminal being connected to said slave switch (T2), and a feedback-loop comprising a feedback-switch (T3) and a third inverter (I3) and being connected to the second inverter input and output terminals.Ģ.